Peter Zijlstra wrote: >> It sets up a per-thread 'VDSO' page and appropriate TLB support. > So traditionally we've always avoided per-thread pages like that. > What makes it worth it on MIPS? MIPS has branch delay slots - it is an instruction after branch which is executed before branch is taken. If branch fails due to FPU unavailability then that instruction should be emulated as well as branch itself. However, MIPS allows to have a customisable coprocessor 2 instructions and it is impractical to emulate it and big amount of other traditional MIPS instructions inside of kernel. So, some per thread space is needed to put instruction into it, enclose it with a return kernel call and switch temporary execution into it. Currently, this space is space at SP register (user stack) but it prevents switching stack as non-executable. Handle another stack set (one stack per thread) in common user map is impractical because of management, scalability and performance difficulties.
