Re: gcc-4.8+ and R10000+

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 09/08/2014 04:11, Miod Vallat wrote:
>> Disassembling a statically-built copy of the "sln" binary generated by
>> glibc's compile phase, there are slight differences in how gcc-4.7 and
>> gcc-4.8 are compiling the __lll_lock_wait_private function.  The key
>> differences in the output asm are
>> this:
> 
> [...]
> 
>> gcc-4.8:
>>    x+4   <START>
>>          ...
>>    x+24  bne     v1,v0,<x+56>
>>          ...
>>    x+32  0x7c03e83b /* rdhwr */
>>    x+36  li      a2,2
>>    x+40  lw      a1,-29832(v1)
>>    x+44  move    a3,zero
>>    x+48  li      v0,4238
>>    x+52  syscall
>> *  x+56  ll      v0,0(s0)
>> *  x+60  li      at,2
>> *  x+64  sc      at,0
> 
> Note how the sc address is no longer 0(s0). Since the address does
> not match the address used in the ll instruction, sc will always
> fail on the R10k.

That would be a typo on my part.  I typed that out by hand and just missed it.  It should read:

gcc-4.8:
   x+4   <START>
         ...
   x+24  bne     v1,v0,<x+56>
         ...
   x+32  0x7c03e83b /* rdhwr */
   x+36  li      a2,2
   x+40  lw      a1,-29832(v1)
   x+44  move    a3,zero
   x+48  li      v0,4238
   x+52  syscall
*  x+56  ll      v0,0(s0)
*  x+60  li      at,2
*  x+64  sc      at,0(s0)
   x+68  beqzl   at,<x+56>
   x+72  nop
   x+76  sync
   x+80  bnez    v0,<x+32>

Thanks!,

-- 
Joshua Kinard
Gentoo/MIPS
kumba@xxxxxxxxxx
4096R/D25D95E3 2011-03-28

"The past tempts us, the present confuses us, the future frightens us.  And our lives slip away, moment by moment, lost in that vast, terrible in-between."

--Emperor Turhan, Centauri Republic


[Index of Archives]     [Linux MIPS Home]     [LKML Archive]     [Linux ARM Kernel]     [Linux ARM]     [Linux]     [Git]     [Yosemite News]     [Linux SCSI]     [Linux Hams]

  Powered by Linux