On Sat, Aug 30, 2014 at 12:57 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > On Friday 29 August 2014 15:14:31 Andrew Bresticker wrote: >> Define a generic MIPS_GIC_IRQ_BASE which is suitable for Malta and >> the upcoming Danube board in <mach-generic/irq.h>. Since Sead-3 is >> different and uses a MIPS_GIC_IRQ_BASE equal to the CPU IRQ base (0), >> define its MIPS_GIC_IRQ_BASE in <mach-sead3/irq.h>. >> >> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx> >> > > Why do you actually have to hardwire an IRQ base? Can't you move > to the linear irqdomain code for DT based MIPS systems yet? Neither Malta nor SEAD-3 use device-tree for interrupts yet, so they still require a hard-coded IRQ base. For boards using device-tree, I stuck with a legacy IRQ domain as it allows most of the existing GIC irqchip code to be reused.
