This adds some code based on code from the Broadcom GPL tar to fix the
reboot problems on BCM4705/BCM4785. I tried rebooting my device for ~10
times and have never seen a problem. This reverts the changes in the
previous commit and adds the real fix as suggested by Rafał.
Setting bit 22 in Reg 22, sel 4 puts the BIU (Bus Interface Unit) into
async mode.
The previous try was this:
commit 316cad5c1d4daee998cd1f83ccdb437f6f20d45c
Author: Hauke Mehrtens <hauke@xxxxxxxxxx>
Date: Mon Jul 28 23:53:57 2014 +0200
MIPS: BCM47XX: make reboot more relaiable
Signed-off-by: Hauke Mehrtens <hauke@xxxxxxxxxx>
---
arch/mips/bcm47xx/setup.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 2b63e7e..ad439c2 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -59,12 +59,21 @@ static void bcm47xx_machine_restart(char *command)
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
- ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
+ if (bcm47xx_bus.ssb.chip_id == 0x4785)
+ write_c0_diag4(1 << 22);
+ ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
+ if (bcm47xx_bus.ssb.chip_id == 0x4785) {
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "sync\n\t"
+ "wait\n\t"
+ ".set\tmips0");
+ }
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
- bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
break;
#endif
}
--
1.9.1
