Ingenic uses the CCA:1 bit to achieve write-combine memory writes. Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx> --- As found in the following git repository https://github.com/IngenicSemiconductor/KERNEL-WARRIOR/blob/master/arch/mips/include/asm/pgtable.h#L342 --- arch/mips/include/asm/pgtable-bits.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 011b0dcf306e..e747bfa0be7e 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#elif defined(CONFIG_MACH_JZ4740) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + #endif #ifndef _CACHE_CACHABLE_NO_WA -- 2.0.0
