Detect the presence of MAAR using the MRP bit in Config5, and record
that presence using a CPU option bit. A cpu_has_maar macro will then
allow code to conditionalise upon the presence of MAARs.
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
---
arch/mips/include/asm/cpu-features.h | 3 +++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/kernel/cpu-probe.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c7d8c99..2101618 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -29,6 +29,9 @@
#ifndef cpu_has_eva
#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
#endif
+#ifndef cpu_has_maar
+#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
+#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 3b8d993..000bb9e 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -363,6 +363,7 @@ enum cpu_type_enum {
#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
+#define MIPS_CPU_MAAR 0x200000000ull /* MAAR(I) registers are present */
/*
* CPU ASE encodings
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d74f957..e818547 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -389,6 +389,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
if (config5 & MIPS_CONF5_EVA)
c->options |= MIPS_CPU_EVA;
+ if (config5 & MIPS_CONF5_MRP)
+ c->options |= MIPS_CPU_MAAR;
return config5 & MIPS_CONF_M;
}
--
2.0.1
