This patch set adds support for setting the irq affinity of the internal
PIC found on SMP capable bcm63xx SoCs.
The PIC has two sets of mask/status registers, wired to two mips IRQs.
Each of the mips irqs can be assigned to a different core, so the irq to
cpu distribution is not fixed, but for simplicity it is assumed that
cpu0 => irq 2, and cpu 1 => irq 3.
Jonas Gorski (10):
MIPS: BCM63XX: add width to __dispatch_internal
MIPS: BCM63XX: move bcm63xx_init_irq down
MIPS: BCM63XX: replace irq dispatch code with a generic version
MIPS: BCM63XX: append irq line to irq_{stat,mask}*
MIPS: BCM63XX: populate irq_{stat,mask}_addr for second cpu
MIPS: BCM63XX: add cpu argument to dispatch internal
MIPS: BCM63XX: protect irq register accesses
MIPS: BCM63XX: wire up the second cpu's irq line
MIPS: BCM63XX: use irq_desc as argument for (un)mask
MIPS: BCM63XX: allow setting affinity for IPIC
arch/mips/bcm63xx/irq.c | 451 +++++++++++++---------
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +-
2 files changed, 278 insertions(+), 189 deletions(-)
--
2.0.0
