Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from the boot CPU. This allows overrides of the CCA using the cca= kernel parameter to take effect on all CPUs for consistency. Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> --- Changes in v2: - Rebase atop v2 of patch 28. --- arch/mips/kernel/cps-vec.S | 11 +++++++---- arch/mips/kernel/smp-cps.c | 8 +++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 1c865ae..6f4f739 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -45,10 +45,12 @@ LEAF(mips_cps_core_entry) /* - * These first 8 bytes will be patched by cps_smp_setup to load the - * base address of the CM GCRs into register v1. + * These first 12 bytes will be patched by cps_smp_setup to load the + * base address of the CM GCRs into register v1 and the CCA to use into + * register s0. */ .quad 0 + .word 0 /* Check whether we're here due to an NMI */ mfc0 k0, CP0_STATUS @@ -139,10 +141,11 @@ icache_done: add a0, a0, t0 dcache_done: - /* Set Kseg0 cacheable, coherent, write-back, write-allocate */ + /* Set Kseg0 CCA to that in s0 */ mfc0 t0, CP0_CONFIG ori t0, 0x7 - xori t0, 0x2 + xori t0, 0x7 + or t0, t0, s0 mtc0 t0, CP0_CONFIG ehb diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 870897d..ec4f115 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -123,9 +123,15 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) } } - /* Patch the start of mips_cps_core_entry to provide the CM base */ + /* + * Patch the start of mips_cps_core_entry to provide: + * + * v0 = CM base address + * s0 = kseg0 CCA + */ entry_code = (u32 *)&mips_cps_core_entry; UASM_i_LA(&entry_code, 3, (long)mips_cm_base); + uasm_i_addiu(&entry_code, 16, 0, cca); dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, (void *)entry_code - (void *)&mips_cps_core_entry); -- 1.8.5.3
