2014-03-24 9:20 GMT-07:00 Maciej W. Rozycki <macro@xxxxxxxxxxxxxx>: > On Mon, 24 Mar 2014, Ralf Baechle wrote: > >> > Some older machines such as the DECStation use a L1 data-cache shift of >> > 2 (value of 4), add a Kconfig symbol for this value so they can express >> > this requirement. >> >> Older DECstations got R2000/R3000 processors which have 16 byte cache >> lines. So a cache shift value of 4 would appear to be right. Maciej? I used arch/mips/include/asm/mach-dec/cpu-feature-overrides.h as a reference and it does look consistent with your boot log snippets (assuming those are only for R2k/R3k processors and not R4k ones?) > > Nope: > > This is a DECstation 5000/1xx > CPU revision is: 00000230 (R3000A) > FPU revision is: 00000340 > [...] > Primary instruction cache 64kB, linesize 4 bytes. > Primary data cache 128kB, linesize 4 bytes. > > or: > > This is a DECstation 5000/2x0 > CPU revision is: 00000230 > FPU revision is: 00000340 > [...] > Primary instruction cache 64kB, linesize 4 bytes. > Primary data cache 64kB, linesize 4 bytes. > > or: > > This is a DECstation 5000/200 > CPU revision is: 00000220 > FPU revision is: 00000320 > [...] > Primary instruction cache 64kB, linesize 4 bytes. > Primary data cache 64kB, linesize 4 bytes. > > or even: > > This is a DECstation 2100/3100 > CPU revision is: 00000220 > FPU revision is: 00000320 > [...] > Primary instruction cache 64kB, linesize 4 bytes. > Primary data cache 64kB, linesize 4 bytes. > > -- so it looks like it's consistent 4 bytes across all the variations > (there's also a /1xx variant with 64kB D$ that I don't have a log from, > but it has the same line size AFAIK). -- Florian
