On Tue, 21 Jan 2014, Florian Fainelli wrote: > When support for the DECStation is enabled, it will default to use a > MIPS R3000 class processor. This will cause an intentional build failure > to popup because MIPS_L1_CACHE_SHIFT and cpu_dcache_line_size() > disagree. Fix this by selecting MIPS_L1_CACHE_SHIFT_2 when we build > targetting a MIPS R3000 CPU to fix that build failure and satisfy all > requirements. Thanks for your contribution. However I just built a pristine ToT LMO kernel for an R3000 DECstation and that went fine, I got no error. Can you provide me with a way to reproduce the problem? I am not opposed to your change per se, it may make sense regardless. However using a value of MIPS_L1_CACHE_SHIFT that is too high results in wasting some memory, but should otherwise be safe I believe, so I'm not really convinced adding this config infrastructure is going to pay off. Maciej
