The code checking whether the core is running the reset vector due to an NMI was mistakenly using the value of the t0 register rather than the k0 register which contains cp0_status. This meant that if t0 happened to have bit 19 set when the core powered up it would mistake the reason as being an NMI, leading to a failure in onlining the CPU. That seems to happen rarely enough that I didn't catch this until I started implementing hotplug & ran a script repeatedly offlining & onlining a CPU. Reviewed-by: Markos Chandras <markos.chandras@xxxxxxxxxx> Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> --- Ideally this would be applied as a fixup for "MIPS: Coherent Processing System SMP implementation". --- arch/mips/kernel/cps-vec.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 95dafcb..40c2abe 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -30,7 +30,7 @@ LEAF(mips_cps_core_entry) /* Check whether we're here due to an NMI */ mfc0 k0, CP0_STATUS - and k0, t0, ST0_NMI + and k0, k0, ST0_NMI beqz k0, not_nmi nop -- 1.8.5.3
