From: Florian Fainelli <florian@xxxxxxxxxxx> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift value of 4) instead of the currently configured 32 bytes L1-cache line size. Reported-by: Daniel Gonzalez <dgcbueu@xxxxxxxxx> Signed-off-by: Florian Fainelli <florian@xxxxxxxxxxx> --- Changes in v2: - rebased on top of john's mips-next-3.14 Changes since v1: - rebased arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 68969d9..beb3766 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -139,6 +139,7 @@ config BCM63XX select SWAP_IO_SPACE select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select MIPS_L1_CACHE_SHIFT_4 help Support for BCM63XX based boards -- 1.8.3.2
