On Sat, Jan 11, 2014 at 11:45 AM, John Crispin <blogic@xxxxxxxxxxx> wrote: > On 10/01/14 21:35, Florian Fainelli wrote: >> >> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift >> value of 4) instead of the currently configured 32 bytes L1-cache line >> size. >> >> Reported-by: Daniel Gonzalez<dgcbueu@xxxxxxxxx> >> Signed-off-by: Florian Fainelli<florian@xxxxxxxxxxx> >> --- >> arch/mips/Kconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >> index 123f7c0..a3fec87 100644 >> --- a/arch/mips/Kconfig >> +++ b/arch/mips/Kconfig >> @@ -139,6 +139,7 @@ config BCM63XX >> select SWAP_IO_SPACE >> select ARCH_REQUIRE_GPIOLIB >> select HAVE_CLK >> + select MIPS_L1_CACHE_SHIFT_4 >> help >> Support for BCM63XX based boards >> > > > Hi Florian, > > why is this not part of 1/3 Because 1/3 is a clean-up/refactoring patch, and this one is a fix (note that BCM63XX did not appear in the default list for "4" in the old code, so it defaulted to "5"). Mixing cleanup and fixes is just bad style. ;) Jonas
