From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx> For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx> Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx> --- arch/mips/include/asm/tlb.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h index 235367ce..4a23493 100644 --- a/arch/mips/include/asm/tlb.h +++ b/arch/mips/include/asm/tlb.h @@ -18,7 +18,9 @@ */ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) +#define UNIQUE_ENTRYHI(idx) \ + ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ + (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) #include <asm-generic/tlb.h> -- 1.8.4.3
