On Tue, Sep 17, 2013 at 11:55:55AM +0100, Markos Chandras wrote:
> On 09/17/13 11:44, Ralf Baechle wrote:
> >On Tue, Sep 17, 2013 at 10:43:25AM +0100, Markos Chandras wrote:
> >
> >>The cache flushing code uses the current_cpu_data macro which
> >>may cause problems in preemptive kernels because it relies on
> >>smp_processor_id() to get the current cpu number. Per cpu-data
> >>needs to be protected so we disable preemption around the flush
> >>caching code. We enable it back when we are about to return.
> >>
> >>Fixes the following problem:
> >>
> >>BUG: using smp_processor_id() in preemptible [00000000] code: kjournald/1761
> >>caller is blast_dcache32+0x30/0x254
> >
> >Just what I feared - these messages popping out from all over the tree.
> >
> >I'd prefer if we change the caller otherwise depending on the platform
> >a single cache flush might involve several preempt_disable/-enable
> >invocations. Something like below.
> >
> >And it also keeps the header file more usable outside the core kernel
> >which Florian's recent zboot a little easier.
> >
>
> Hi Ralf,
>
> Changing the caller instead of the function in the header file looks
> good to me. Thanks for fixing it.
I think in the end the patch below is the better way of fixing it.
Ralf
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
arch/mips/include/asm/cpu-info.h | 1 +
arch/mips/include/asm/r4kcache.h | 16 ++++++++--------
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 41401d8..21c8e29 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -84,6 +84,7 @@ struct cpuinfo_mips {
extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+#define boot_cpu_data cpu_data[0]
extern void cpu_probe(void);
extern void cpu_report(void);
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index a0b2650..be52f27 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -344,10 +344,10 @@ static inline void invalidate_tcache_page(unsigned long addr)
static inline void blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
- unsigned long end = start + current_cpu_data.desc.waysize; \
- unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
- unsigned long ws_end = current_cpu_data.desc.ways << \
- current_cpu_data.desc.waybit; \
+ unsigned long end = start + boot_cpu_data.desc.waysize; \
+ unsigned long ws_inc = 1UL << boot_cpu_data.desc.waybit; \
+ unsigned long ws_end = boot_cpu_data.desc.ways << \
+ boot_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
__##pfx##flush_prologue \
@@ -376,12 +376,12 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
\
static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
{ \
- unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
+ unsigned long indexmask = boot_cpu_data.desc.waysize - 1; \
unsigned long start = INDEX_BASE + (page & indexmask); \
unsigned long end = start + PAGE_SIZE; \
- unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
- unsigned long ws_end = current_cpu_data.desc.ways << \
- current_cpu_data.desc.waybit; \
+ unsigned long ws_inc = 1UL << boot_cpu_data.desc.waybit; \
+ unsigned long ws_end = boot_cpu_data.desc.ways << \
+ boot_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
__##pfx##flush_prologue \
