Hi Mark,
Thanks for the review, I will send a V2 tomorrow, I want to verify my
changes on real HW first.
a few comments inline ...
There is presumably a maximum transfer size here from the FIFO that is
holding the data?
The hardware is not running in DMA/IRQ mode and hence it can only
read/write 1 byte at a time.
Set min_speed_hz in the spi_master and the core will check this for you.
it seems that min_speed is not handled by the core yet. I saw several
drivers do minimum speed testing. I am leaving this code in the driver
until there is a generic minimum speed check
clk_prepare_enable(), and it'd be nice to use runtime PM and enable the
clock only when doing transfers though that's not essential.
The clock is free running and always running.
John
