On Thu, Aug 08, 2013 at 11:07:23AM +0200, John Crispin wrote: > Comparing the upstream code with the Lantiq UGW kernel we see that burst length > should be set to 4 bytes. > > Signed-off-by: John Crispin <blogic@xxxxxxxxxxx> > --- > arch/mips/lantiq/xway/dma.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c > index 08f7ebd..ccf1451 100644 > --- a/arch/mips/lantiq/xway/dma.c > +++ b/arch/mips/lantiq/xway/dma.c > @@ -48,6 +48,7 @@ > #define DMA_IRQ_ACK 0x7e /* IRQ status register */ > #define DMA_POLL BIT(31) /* turn on channel polling */ > #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ > +#define DMA_4W_BURST BIT(2) /* 4 word burst length */ > #define DMA_2W_BURST BIT(1) /* 2 word burst length */ that's wrong, it's not BIT(x), but x itself. 1 means 2 word burst 2 means 4 word burst 3 means 8 word burst Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
