On Mon, 29 Jul 2013, Florian Fainelli wrote: > It is not clear to me whether this secondary cevt is also a r4k-cevt > device, or if it is something else? If the IRQ is shared, is there any > way to differentiate the ralink cevt from the r4k cevt, such that both > could request the same irq with the IRQF_SHARED flag? As from rev. 2 of the MIPS architecture processors are required to implement a CP0.Cause.TI bit to indicate a CP0.Count/CP0.Compare timer interrupt pending -- so it may all bail down to figuring out what MIPS architecture level this SoC implements. FWIW. HTH. Maciej
