On Fri, Jun 28, 2013 at 11:15 PM, Steven J. Hill <Steven.Hill@xxxxxxxxxx> wrote: > From: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > > Original idea from <http://patchwork.linux-mips.org/patch/4701/>. > > Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Acked-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx> > --- > arch/mips/cavium-octeon/csrc-octeon.c | 1 + > arch/mips/include/asm/cpu-features.h | 4 - > arch/mips/include/asm/cpu-type.h | 196 +++++++++++++++++++++++++++++++++ > arch/mips/kernel/cpu-probe.c | 3 +- > arch/mips/kernel/idle.c | 3 +- > arch/mips/kernel/time.c | 1 + > arch/mips/kernel/traps.c | 3 +- > arch/mips/mm/c-octeon.c | 6 +- > arch/mips/mm/c-r4k.c | 14 +-- > arch/mips/mm/dma-default.c | 8 ++ > arch/mips/mm/page.c | 1 + > arch/mips/mm/sc-mips.c | 3 +- > arch/mips/mm/tlb-r4k.c | 1 + > arch/mips/mm/tlbex.c | 1 + > arch/mips/oprofile/common.c | 1 + > arch/mips/oprofile/op_model_mipsxx.c | 1 + > 16 files changed, 230 insertions(+), 17 deletions(-) > create mode 100644 arch/mips/include/asm/cpu-type.h > > diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c > index 0219395..b752c4e 100644 > --- a/arch/mips/cavium-octeon/csrc-octeon.c > +++ b/arch/mips/cavium-octeon/csrc-octeon.c > @@ -12,6 +12,7 @@ > #include <linux/smp.h> > > #include <asm/cpu-info.h> > +#include <asm/cpu-type.h> > #include <asm/time.h> > > #include <asm/octeon/octeon.h> > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 1dc0860..51680d1 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -13,10 +13,6 @@ > #include <asm/cpu-info.h> > #include <cpu-feature-overrides.h> > > -#ifndef current_cpu_type > -#define current_cpu_type() current_cpu_data.cputype > -#endif > - > /* > * SMP assumption: Options of CPU 0 are a superset of all processors. > * This is true for all known MIPS systems. > diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h > new file mode 100644 > index 0000000..143610e > --- /dev/null > +++ b/arch/mips/include/asm/cpu-type.h > @@ -0,0 +1,196 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2003, 2004 Ralf Baechle > + * Copyright (C) 2004 Maciej W. Rozycki > + */ > +#ifndef __ASM_CPU_TYPE_H > +#define __ASM_CPU_TYPE_H > + > +#include <linux/compiler.h> > + > +static inline int __pure current_cpu_type(void) > +{ > + const int cpu_type = current_cpu_data.cputype; > + > + switch (cpu_type) { > +#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \ > + defined(CONFIG_SYS_HAS_CPU_LOONGSON2F) > + case CPU_LOONGSON2: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B > + case CPU_LOONGSON1: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 > + case CPU_4KC: > + case CPU_ALCHEMY: > + case CPU_PR4450: > + case CPU_BMIPS32: > + case CPU_JZRISC: > +#endif > + > +#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \ > + defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) > + case CPU_4KEC: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2 > + case CPU_4KSC: > + case CPU_24K: > + case CPU_34K: > + case CPU_1004K: > + case CPU_74K: > + case CPU_M14KC: > + case CPU_M14KEC: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 > + case CPU_5KC: > + case CPU_5KE: > + case CPU_20KC: > + case CPU_25KF: > + case CPU_SB1: > + case CPU_SB1A: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2 > + /* > + * All MIPS64 R2 processors have their own special symbols. That is, > + * there currently is no pure R2 core > + */ > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R3000 > + case CPU_R2000: > + case CPU_R3000: > + case CPU_R3000A: > + case CPU_R3041: > + case CPU_R3051: > + case CPU_R3052: > + case CPU_R3081: > + case CPU_R3081E: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_TX39XX > + case CPU_TX3912: > + case CPU_TX3922: > + case CPU_TX3927: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_VR41XX > + case CPU_VR41XX: > + case CPU_VR4111: > + case CPU_VR4121: > + case CPU_VR4122: > + case CPU_VR4131: > + case CPU_VR4133: > + case CPU_VR4181: > + case CPU_VR4181A: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R4300 > + case CPU_R4300: > + case CPU_R4310: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R4X00 > + case CPU_R4000PC: > + case CPU_R4000SC: > + case CPU_R4000MC: > + case CPU_R4200: > + case CPU_R4400PC: > + case CPU_R4400SC: > + case CPU_R4400MC: > + case CPU_R4600: > + case CPU_R4700: > + case CPU_R4640: > + case CPU_R4650: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_TX49XX > + case CPU_TX49XX: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R5000 > + case CPU_R5000: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R5432 > + case CPU_R5432: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R5500 > + case CPU_R5500: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R6000 > + case CPU_R6000: > + case CPU_R6000A: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_NEVADA > + case CPU_NEVADA: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R8000 > + case CPU_R8000: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_R10000 > + case CPU_R10000: > + case CPU_R12000: > + case CPU_R14000: > +#endif > +#ifdef CONFIG_SYS_HAS_CPU_RM7000 > + case CPU_RM7000: > + case CPU_SR71000: > +#endif > +#ifdef CONFIG_SYS_HAS_CPU_RM9000 > + case CPU_RM9000: > +#endif > +#ifdef CONFIG_SYS_HAS_CPU_SB1 > + case CPU_SB1: > + case CPU_SB1A: > +#endif > +#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON > + case CPU_CAVIUM_OCTEON: > + case CPU_CAVIUM_OCTEON_PLUS: > + case CPU_CAVIUM_OCTEON2: > +#endif > + > +#ifdef CONFIG_SYS_HAS_CPU_BMIPS3300 > + case CPU_BMIPS3300: > +#endif This will break SSB based BCM47XX systems and older BCM63XX, as neither currently select SYS_HAS_CPU_BMIPS3300, but do have BMIPS3300 CPUs (for BCM63XX I am working on a patchset that cleans up the BMIPS code and fixes this, but it isn't finished yet). Jonas
