On Thu, 20 Jun 2013, Ralf Baechle wrote: > So I've removed it again for now. > > Maciej, I wonder why does gas in MIPS III/IV mode accept > > dmfc0 $reg1, $cp0reg > > but not > > dmfc0 $reg1, $cp0reg, 0 > > The generated code is the same after all. Same for MIPS I/II mode and > mfc0. The <sel> operand and instruction field was only added to these instructions with the MIPS64 ISA (MIPS32 ISA for MFC0/MTC0). Previously processors did not decode this field and consequently the assembler notation only supports two operands. Since AFAICT the offending pieces are macros I suggest simply dumping the redundant ", 0" part, the two-argument form is as you've observed equivalent. Maciej
