Hello.
On 20-06-2013 9:57, Steven J. Hill wrote:
From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.
Change-Id: Idef3b6abbb63a1bbd5e153c6110a979fa7bd5896
Sigh...
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
Acked-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
---
arch/mips/mm/tlbex.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d9969d2..5ef426c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1922,6 +1922,11 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_nop(&p);
uasm_i_tlbr(&p);
+#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
Suggesting to use if (!IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON)) to
avoid #ifdef...
+ /* hazard barrier after TLBR but before read EntryLo */
+ if (cpu_has_mips_r2)
+ uasm_i_ehb(&p);
+#endif
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1976,6 +1981,11 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_nop(&p);
uasm_i_tlbr(&p);
+#if !defined(CONFIG_CPU_CAVIUM_OCTEON)
Same here.
+ /* hazard barrier after TLBR but before read EntryLo */
+ if (cpu_has_mips_r2)
+ uasm_i_ehb(&p);
+#endif
WBR, Sergei
