On Sat, Jun 15, 2013 at 05:34:40PM +0100, Paul Burton wrote: > Writing a value to a WatchLo* register creates an execution hazard, so > if its value is then read before that hazard is cleared then said value > may be invalid. The mips_probe_watch_registers function must therefore > clear the execution hazard between setting the match bits in a WatchLo* > register & reading the register back in order to check which are set. > > This fixes intermittent incorrect watchpoint register probing on some > MIPS cores such as interAptiv & proAptiv. Obviously correct. Did somebody once have a tool to test for this kind of back-to-back cp0 issues? Ralf
