Most newer BCM63XX SoCs after BCM6358 use a BMIPS4350 CPU with SMP support. This patchset allows BCM6368 and BCM6362 to boot a SMP kernel (both tested, as well as (not yet upstreamed) BCM63268). BCM6328 has its second core only in a few variants enabled, but this can be probed at runtime. BCM6358 is intentionally skipped because it shares a single TLB for both cores/threads, which requires implementing locking for TLB accesses, and ain't nobody got time for that. The internal interrupt controller supports routing IRQs to both CPUs, and support will be added in a later patchset. For now all hardware interrupts will go to CPU0. Totally unscientific OpenSSL benchmarking shows a nice ~90% speed increase when enabling the second core. No idea about the FIXME in 1/2, never had a problem with it so I left it in place as to have it documented. Changes V1 -> V2: * removed already applied patches * added a check for SMP availability on BCM6328 * changed #ifdef FOO to if (IS_ENABLED(FOO)) Jonas Gorski (1): MIPS: BCM63XX: Enable second core SMP on BCM6328 if available Kevin Cernekee (1): MIPS: BCM63XX: Add SMP support to prom.c arch/mips/bcm63xx/prom.c | 45 +++++++++++++++++++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 7 ++++ 3 files changed, 54 insertions(+) -- 1.7.10.4
