On Sat, Jun 8, 2013 at 8:18 PM, Maciej W. Rozycki <macro@xxxxxxxxxxxxxx> wrote:
> On Thu, 23 May 2013, Manuel Lauss wrote:
>
>> Only an interrupt can wake the core from 'wait', enable interrupts
>> locally before executing 'wait'.
>>
>> Signed-off-by: Manuel Lauss <manuel.lauss@xxxxxxxxx>
>> ---
>> Ralf made me aware of the race in between enabling interrupts and
>> entering wait. While this patch does not eliminate it, it shrinks it
>> to 1 instruction. It's not perfect, but lets Alchemy boot until a
>> more sophisticated solution (like __r4k_wait) can be implemented
>> without having to duplicate the interrupt exception handler.
>
> I suggest double-checking with Alchemy documentation, but I doubt there
> is a race here, the write-back pipeline stage of MTC0 should overlap with
> the execution stage of WAIT, so assuming interrupts were previously
> disabled there should be no window between setting CP0.Status.IE and
> executing WAIT that would permit an interrrupt exception to be taken.
That was my thinking as well. The Alchemy manuals (at least the ones I have)
don't specify the stage where c0 writes complete or 'wait' executes, but the
wording on how and when exceptions are raised makes me believe the
scheme above is race-free.
> There is a bug in your change however.
[...]
> You can't just take $8 away under the feet of GCC without telling the
> compiler, it may be storing some data there across the asm. Rather than
> picking an arbitrary register as a clobber I suggest using an output
> register constraint associated with a scratch variable (depending on
> register usage GCC may possibly be able to reuse the same register both
> for input and for output).
I've fixed that, and sent out a new patch.
Thank you very much!
Manuel
