On 05/20/2013 11:36 AM, Maciej W. Rozycki wrote:
On Mon, 20 May 2013, Sanjay Lal wrote:
(1) Newer versions of the MIPS architecture define scratch registers for
just this purpose, but since we have to support standard MIPS32R2
processors, we use the DDataLo Register (CP0 Register 28, Select 3) as a
scratch register to save k0 and save k1 @ a known offset from EBASE.
That's rather risky as the implementation of this register (and its
presence in the first place) is processor-specific. Do you maintain a
list of PRId values the use of this register is safe with?
FWIW: The MIPS-VZ architecture module requires the presence of CP0
scratch registers that can be used for this in the exception handlers
without having to worry about using these implementation dependent
registers. For the trap-and-emulate only version, there really is no
choice other than to re-purpose some of the existing CP0 registers.
David Daney
