local_flush_icache_range flushed whereever *stop was pointing to, which
might not necessarily be a valid memory address. This caused TLB misses
at least on BCM63XX, failing early.
Instead move the local_flush_icache_range into the loop as it was
probably intended so it will flush each modified instruction's address.
This breakage was introduced with d532f3d26716a39dfd4b88d687bd344fbe77e390
("MIPS: Allow ASID size to be determined at boot time.").
Signed-off-by: Jonas Gorski <jogo@xxxxxxxxxxx>
---
arch/mips/mm/tlbex.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a188d42..4d46d37 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -332,8 +332,9 @@ static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop,
*ip = i_const;
}
#endif
+ local_flush_icache_range((unsigned long)ip,
+ (unsigned long)ip + sizeof(*ip));
}
- local_flush_icache_range((unsigned long)*p, (unsigned long)((*p) + 1));
}
#define asid_insn_fixup(section, const) \
--
1.7.10.4
