Re: [PATCH V2 02/16] MIPS: ralink: fix RT305x clock setup

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2013.04.12. 9:27 keltezéssel, John Crispin írta:
> Add a few missing clocks.
> 
> Signed-off-by: John Crispin <blogic@xxxxxxxxxxx>
> ---
>  arch/mips/ralink/rt305x.c |   13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> index 0a4bbdc..64a0336 100644
> --- a/arch/mips/ralink/rt305x.c
> +++ b/arch/mips/ralink/rt305x.c
> @@ -123,7 +123,8 @@ struct ralink_pinmux gpio_pinmux = {
>  
>  void __init ralink_clk_init(void)
>  {
> -	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
> +	unsigned long cpu_rate, sys_rate, wdt_rate,
> +			uart_rate, wmac_rate = 40000000;

Moving the wmac_rate definition into a separate line would make the code more
readable.

>  	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
>  
>  	if (soc_is_rt305x() || soc_is_rt3350()) {
> @@ -176,11 +177,21 @@ void __init ralink_clk_init(void)
>  		BUG();
>  	}
>  
> +	if (soc_is_rt3352() || soc_is_rt5350()) {
> +		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
> +
> +		if (!(val & RT3352_CLKCFG0_XTAL_SEL))

Given the fact that the definition of RT3352_SYSC_REG_SYSCFG0 and
RT3352_CLKCFG0_XTAL_SEL is added in a later patch, this code causes a build error?

> +			wmac_rate = 20000000;
> +	}
> +
>  	ralink_clk_add("cpu", cpu_rate);
>  	ralink_clk_add("10000b00.spi", sys_rate);
>  	ralink_clk_add("10000100.timer", wdt_rate);
> +	ralink_clk_add("10000120.watchdog", wdt_rate);
>  	ralink_clk_add("10000500.uart", uart_rate);
>  	ralink_clk_add("10000c00.uartlite", uart_rate);
> +	ralink_clk_add("10100000.ethernet", sys_rate);
> +	ralink_clk_add("wmac@10180000", wmac_rate);

Should not this be "10180000.wmac"?

>  }
>  
>  void __init ralink_of_remap(void)
> 

-Gabor


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