-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/30/2013 12:24 AM, Huacai Chen wrote: > Loongson-3 maintains cache coherency by hardware. So we introduce a cpu > feature named cpu_has_coherent_cache and use it to modify MIPS's cache > flushing functions. > > Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> Signed-off-by: Hongliang Tao > <taohl@xxxxxxxxxx> Signed-off-by: Hua Yan <yanh@xxxxxxxxxx> --- > arch/mips/include/asm/cacheflush.h | 6 +++++ > arch/mips/include/asm/cpu-features.h | 3 ++ > .../asm/mach-loongson/cpu-feature-overrides.h | 6 +++++ > arch/mips/mm/c-r4k.c | 21 > ++++++++++++++++++- 4 files changed, 34 insertions(+), 2 deletions(-) > Hello. This patch masks the problem that you are not properly probing your L1 caches to start with. For some reason in 'probe_pcache()' you reach the default case where the primary data cache is marked as having aliases. If your CPU truly is HW coherent with no aliases, then MIPS_CACHE_ALIASES should never get set. Fixing this would eliminate the 'arch/mips/include/asm/cacheflush.h' and 'arch/mips/mm/c-r4k.c' changes completely. There is no need to add more CPU feature bits for this single platform, thus changes to 'cpu-features.h' and 'cpu-features-overrides.h' will not be accepted. Also, please do not copy the <linux-kernel@xxxxxxxxxxxxxxx> mailing list unless your patch touches files outside of 'arch/mips' in order to cut down traffic on an already busy list. Thanks. Steve - ----- <sjhill@xxxxxxxx> <Steven.Hill@xxxxxxxxxx> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlFm7WAACgkQgyK5H2Ic36eHuwCeKZjp1+arkoheEpeuzjJkQskN /7MAnig14A03hWxRvfqDOMbMFKXpZBO8 =HRPU -----END PGP SIGNATURE-----
