On Mon, Jan 14, 2013 at 09:41:56PM +0530, Jayachandran C wrote: > Since we now use r4k cache code for Netlogic XLP, it is > better to split L1 icache among the active threads, so that > threads won't step on each other while flushing icache. > > The L1 dcache is already split among the threads in the core. It's a bit orthogonal to your patch but you may want to look at adding support for SYS_SUPPORTS_SCHED_SMT which scheduler support for SMT that is tries to schedule threads in a shared cache friendly way. See 0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b [[MIPS] MT: Scheduler support for SMT]. Ralf
