This set of patches enable the use of scratch registers on XLR/XLS and XLP (cop0 reg 22, sel 0-7) to optimize the genearted TLB handlers. The current code assumes scratch is 31, which is fixed by the first patch. The second patch enables use of a scratch register when it is available, even on a 32-bit or non-r2 platform. The third patch is a cleanup to consolidate all the defines needed into one file, this patch does not have any change in logic. In the earlier scheme, if MIPS_PGD_C0_CONTEXT was defined, the CP0 CONTEXT register or a scratch register would contain the current PGD, and the XCONTEXT would contain the smp_processor_id shifted to index pointers. In the new scheme, the behavior when MIPS_PGD_C0_CONTEXT is defined remains the same. But when it is not defined, we tries to allocate a scratch register for the current pgd, the smp processor id remains in CONTEXT. The additional change is generate tlbmiss_handler_setup_pgd() function that stores pgd even when MIPS_PGD_C0_CONTEXT is not defined. This function will save the PGD in pgd_current[] and also in the scratch register if one has been allocated. Comments/testing welcome. Thanks, JC. Jayachandran C (3): MIPS: Allow platform specific scratch registers MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT MIPS: Move definition of SMP processor id register to header file arch/mips/include/asm/mmu_context.h | 26 ++--- arch/mips/include/asm/stackframe.h | 25 ++--- arch/mips/include/asm/thread_info.h | 33 +++++- arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kernel/genex.S | 1 - arch/mips/mm/tlbex.c | 188 ++++++++++++++++++----------------- 6 files changed, 146 insertions(+), 128 deletions(-) -- 1.7.9.5
