On Wed, 31 Oct 2012, Sanjay Lal wrote: > diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h > index cb41af5..59c9245 100644 > --- a/arch/mips/include/asm/stackframe.h > +++ b/arch/mips/include/asm/stackframe.h > @@ -30,7 +30,7 @@ > #define STATMASK 0x1f > #endif > > -#ifdef CONFIG_MIPS_MT_SMTC > +#if defined(CONFIG_MIPS_MT_SMTC) || defined (CONFIG_MIPS_HW_FIBERS) > #include <asm/mipsmtregs.h> > #endif /* CONFIG_MIPS_MT_SMTC */ > > @@ -162,9 +162,9 @@ > .set noat > .set reorder > mfc0 k0, CP0_STATUS > - sll k0, 3 /* extract cu0 bit */ > + andi k0,k0,0x10 /* check user mode bit*/ > .set noreorder > - bltz k0, 8f > + beq k0, $0, 8f > move k1, sp > .set reorder > /* Called from user mode, new stack. */ Any reason this is needed for? If so, then given that this is generic code a corresponding piece has to be added to support the MIPS I ISA processors that have the user mode bit in a different location. Presumably you'll update all the other places that fiddle with CP0.Status.CU0 too? Maciej
