On Nov 1, 2012, at 11:24 AM, Avi Kivity wrote: > On 10/31/2012 05:19 PM, Sanjay Lal wrote: >> Currently, the following instructions are translated: >> - CACHE (indexed) >> - CACHE (va based): translated to a synci, overkill on D-CACHE operations, but still much faster than a trap. >> - mfc0/mtc0: the virtual COP0 registers for the guest are implemented as 2-D array >> [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0. >> mfc0/mtc0 operations are transformed to load/stores. >> > > Seems to be more of binary patching, yes? Binary translation usually > involves hiding the translated code so the guest is not able to detect > that it is patched. Now that you mention it, I think binary patching would be more applicable. If the "self-aware" guest ever compared the code it would realize that it has changed. Regards Sanjay
