Adds a new cpu type for the JZ4750D to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4750D SoC. Signed-off-by: Antony Pavlov <antonynpavlov@xxxxxxxxx> --- arch/mips/include/asm/bootinfo.h | 1 + arch/mips/include/asm/mach-jz4750d/base.h | 12 ++++++++++++ arch/mips/include/asm/mach-jz4750d/war.h | 25 +++++++++++++++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 arch/mips/include/asm/mach-jz4750d/base.h create mode 100644 arch/mips/include/asm/mach-jz4750d/war.h diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 7a51d87..1d7fea3 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -76,6 +76,7 @@ */ #define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */ #define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */ +#define MACH_INGENIC_JZ4750D 3 /* JZ4750D SOC */ extern char *system_type; const char *get_system_type(void); diff --git a/arch/mips/include/asm/mach-jz4750d/base.h b/arch/mips/include/asm/mach-jz4750d/base.h new file mode 100644 index 0000000..723b1d0 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4750d/base.h @@ -0,0 +1,12 @@ +#ifndef __ASM_MACH_JZ4750D_BASE_H__ +#define __ASM_MACH_JZ4750D_BASE_H__ + +#define JZ4750D_CPM_BASE_ADDR 0x10000000 +#define JZ4750D_INTC_BASE_ADDR 0x10001000 +#define JZ4750D_WDT_BASE_ADDR 0x10002000 +#define JZ4750D_TCU_BASE_ADDR 0x10002010 +#define JZ4750D_RTC_BASE_ADDR 0x10003000 +#define JZ4750D_UART0_BASE_ADDR 0x10030000 +#define JZ4750D_UART1_BASE_ADDR 0x10031000 + +#endif diff --git a/arch/mips/include/asm/mach-jz4750d/war.h b/arch/mips/include/asm/mach-jz4750d/war.h new file mode 100644 index 0000000..7bbad65 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4750d/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@xxxxxxxxxxxxxx> + */ +#ifndef __ASM_MIPS_MACH_JZ4750D_WAR_H +#define __ASM_MIPS_MACH_JZ4750D_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JZ4750D_WAR_H */ -- 1.7.10.4
