On 12/30/2011 12:31 AM, Xiangfu Liu wrote:
I meet the same problem on MIPS jz4740, here is the step I try to find
out the problem:
1. when I direct run 'hwclock' it will give
"select() to /dev/rtc0 to wait for clock tick timed out"
attachment 'hwclock.time.out' is the strace log
2. run 'rtctest' program. it works fine. the output is here[1]
3. after 'rtctest', run 'hwclock' again. then it works fine
attachment 'hwclock.wors' is the strace log
without 'rtctest' run first. 'hwclock' never works.
the hwclock works fine in 2.6.27.6, failed under '3.0.0'
Please give me some tips how to fix this problem. shoule I modify the
driver code
or is that relate to 'CONFIG_RTC_INTF_DEV_UIE_EMUL'?
Sorry I missed this email originally, and thank you for pinging me.
Is CONFIG_RTC_INTF_DEV_UIE_EMUL set in the config you're seeing this
with? Does disabling it change the behavior?
Just a shot in the dark, but does the following help at all?
thanks
-john
Signed-off-by: John Stultz<john.stultz@xxxxxxxxxx>
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
index 05ab227..c6c81ba 100644
--- a/drivers/rtc/rtc-jz4740.c
+++ b/drivers/rtc/rtc-jz4740.c
@@ -171,7 +171,8 @@ static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct jz4740_rtc *rtc = dev_get_drvdata(dev);
- return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
+ return jz4740_rtc_ctrl_set_bits(rtc,
+ JZ_RTC_CTRL_AE |JZ_RTC_CTRL_AF_IRQ, enable);
}
static struct rtc_class_ops jz4740_rtc_ops = {