Since the read address and the write address are different, so i am worry about
the out-of-order execution. I just want make sure the read instruction *not*
ahead of that write instruction.
I didn't know about the detail principle of out-of-order execution on this SOC, and
i didn't know the read for different address will also complete after all preceeding
writes have completed.
在 2011年12月8日 下午9:08，Ralf Baechle <ralf@xxxxxxxxxxxxxx>写道：
On Thu, Dec 01, 2011 at 04:44:38PM +0800, zhzhl555@xxxxxxxxx wrote:Why the SYNC instruction? This is an uncached write and on all MIPS CPUs
> + writel(t, SYS_TOYWRITE1);
> + __asm__ volatile ("sync");
> + c = 0x10000;
> + while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
> + usleep_range(1000, 3000);
the SYNC instruction will only make sure the write has left the CPU's
write buffers. There is no guarantee that by the time the SYNC has completed
the write has actually reached its destination. If that is what you want,
read something from device. Reads will only complete after all preceeding
writes have completed.
In this driver all instances of SYNC instructions are followed by polling
loops reading from the RTC which means all SYNCs should be unnecessary.
Or?
Ralf
