XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache flushes. Signed-off-by: Jayachandran C <jayachandranc@xxxxxxxxxxxxxxxxx> --- .../asm/mach-netlogic/cpu-feature-overrides.h | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h index 3b72827..3780743 100644 --- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h @@ -25,13 +25,12 @@ #define cpu_has_llsc 1 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_ic_fills_f_dc 1 #define cpu_has_dsp 0 #define cpu_has_mipsmt 0 #define cpu_has_userlocal 0 -#define cpu_icache_snoops_remote_store 0 +#define cpu_icache_snoops_remote_store 1 -#define cpu_has_nofpuex 0 #define cpu_has_64bits 1 #define cpu_has_mips32r1 1 -- 1.7.4.1
