On 10 June 2011 23:47, Maxime Bizon <mbizon@xxxxxxxxxx> wrote:
> Signed-off-by: Maxime Bizon <mbizon@xxxxxxxxxx>
> ---
> Âarch/mips/bcm63xx/Kconfig             |  Â4 +
> Âarch/mips/bcm63xx/clk.c              |  70 +++++++++++++-
> Âarch/mips/bcm63xx/cpu.c              |  76 ++++++++++++---
> Âarch/mips/bcm63xx/dev-uart.c           Â|  Â2 +-
> Âarch/mips/bcm63xx/irq.c              |  16 +++
> Âarch/mips/bcm63xx/prom.c             Â|  Â7 +-
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h Â| Â 99 +++++++++++++++++++
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | Â Â2 +
> Âarch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | Â106 ++++++++++++++++++++-
> Âarch/mips/include/asm/mach-bcm63xx/ioremap.h   Â|  Â4 +
> Âarch/mips/pci/pci-bcm63xx.c            |  Â4 +-
> Â11 files changed, 364 insertions(+), 26 deletions(-)
>
> diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
> index fb177d6..6b1b9ad 100644
> --- a/arch/mips/bcm63xx/Kconfig
> +++ b/arch/mips/bcm63xx/Kconfig
> @@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
> Âconfig BCM63XX_CPU_6358
> Â Â Â Âbool "support 6358 CPU"
> Â Â Â Âselect HW_HAS_PCI
> +
> +config BCM63XX_CPU_6368
> + Â Â Â bool "support 6368 CPU"
> + Â Â Â select HW_HAS_PCI
> Âendmenu
>
> Âsource "arch/mips/bcm63xx/boards/Kconfig"
> diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
> index 2c68ee9..9d57c71 100644
> --- a/arch/mips/bcm63xx/clk.c
> +++ b/arch/mips/bcm63xx/clk.c
> @@ -10,6 +10,7 @@
> Â#include <linux/mutex.h>
> Â#include <linux/err.h>
> Â#include <linux/clk.h>
> +#include <linux/delay.h>
> Â#include <bcm63xx_cpu.h>
> Â#include <bcm63xx_io.h>
> Â#include <bcm63xx_regs.h>
> @@ -113,6 +114,34 @@ static struct clk clk_ephy = {
> Â};
>
> Â/*
> + * Ethernet switch clock
> + */
> +static void enetsw_set(struct clk *clk, int enable)
> +{
> + Â Â Â if (!BCMCPU_IS_6368())
> + Â Â Â Â Â Â Â return;
> + Â Â Â bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
> + Â Â Â Â Â Â Â Â Â Â Â CKCTL_6368_SWPKT_USB_EN |
> + Â Â Â Â Â Â Â Â Â Â Â CKCTL_6368_SWPKT_SAR_EN, enable);
> + Â Â Â if (enable) {
> + Â Â Â Â Â Â Â u32 val;
> +
> + Â Â Â Â Â Â Â /* reset switch core afer clock change */
> + Â Â Â Â Â Â Â val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â val &= ~SOFTRESET_6368_ENETSW_MASK;
> + Â Â Â Â Â Â Â bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â msleep(10);
> + Â Â Â Â Â Â Â val |= SOFTRESET_6368_ENETSW_MASK;
> + Â Â Â Â Â Â Â bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â msleep(10);
> + Â Â Â }
> +}
> +
> +static struct clk clk_enetsw = {
> +    .set  Â= enetsw_set,
> +};
> +
> +/*
> Â* PCM clock
> Â*/
> Âstatic void pcm_set(struct clk *clk, int enable)
> @@ -131,9 +160,10 @@ static struct clk clk_pcm = {
> Â*/
> Âstatic void usbh_set(struct clk *clk, int enable)
> Â{
> - Â Â Â if (!BCMCPU_IS_6348())
> - Â Â Â Â Â Â Â return;
> - Â Â Â bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
> + Â Â Â if (BCMCPU_IS_6348())
> + Â Â Â Â Â Â Â bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
> + Â Â Â else if (BCMCPU_IS_6368())
> + Â Â Â Â Â Â Â bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
> Â}
>
> Âstatic struct clk clk_usbh = {
> @@ -162,6 +192,36 @@ static struct clk clk_spi = {
> Â};
>
> Â/*
> + * XTM clock
> + */
> +static void xtm_set(struct clk *clk, int enable)
> +{
> + Â Â Â if (!BCMCPU_IS_6368())
> + Â Â Â Â Â Â Â return;
> +
> + Â Â Â bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
> + Â Â Â Â Â Â Â Â Â Â Â CKCTL_6368_SWPKT_SAR_EN, enable);
> +
> + Â Â Â if (enable) {
> + Â Â Â Â Â Â Â u32 val;
> +
> + Â Â Â Â Â Â Â /* reset sar core afer clock change */
> + Â Â Â Â Â Â Â val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â val &= ~SOFTRESET_6368_SAR_MASK;
> + Â Â Â Â Â Â Â bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â mdelay(1);
> + Â Â Â Â Â Â Â val |= SOFTRESET_6368_SAR_MASK;
> + Â Â Â Â Â Â Â bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> + Â Â Â Â Â Â Â mdelay(1);
> + Â Â Â }
> +}
> +
> +
> +static struct clk clk_xtm = {
> +    .set  Â= xtm_set,
> +};
> +
> +/*
> Â* Internal peripheral clock
> Â*/
> Âstatic struct clk clk_periph = {
> @@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
> Â Â Â Â Â Â Â Âreturn &clk_enet0;
> Â Â Â Âif (!strcmp(id, "enet1"))
> Â Â Â Â Â Â Â Âreturn &clk_enet1;
> + Â Â Â if (!strcmp(id, "enetsw"))
> + Â Â Â Â Â Â Â return &clk_enetsw;
> Â Â Â Âif (!strcmp(id, "ephy"))
> Â Â Â Â Â Â Â Âreturn &clk_ephy;
> Â Â Â Âif (!strcmp(id, "usbh"))
> Â Â Â Â Â Â Â Âreturn &clk_usbh;
> Â Â Â Âif (!strcmp(id, "spi"))
> Â Â Â Â Â Â Â Âreturn &clk_spi;
> + Â Â Â if (!strcmp(id, "xtm"))
> + Â Â Â Â Â Â Â return &clk_xtm;
> Â Â Â Âif (!strcmp(id, "periph"))
> Â Â Â Â Â Â Â Âreturn &clk_periph;
> Â Â Â Âif (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
> diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
> index 027ac30..3ea2533 100644
> --- a/arch/mips/bcm63xx/cpu.c
> +++ b/arch/mips/bcm63xx/cpu.c
> @@ -66,6 +66,15 @@ static const int bcm96358_irqs[] = {
>
> Â};
>
> +static const unsigned long bcm96368_regs_base[] = {
> + Â Â Â __GEN_CPU_REGS_TABLE(6368)
> +};
> +
> +static const int bcm96368_irqs[] = {
> + Â Â Â __GEN_CPU_IRQ_TABLE(6368)
> +
> +};
> +
> Âu16 __bcm63xx_get_cpu_id(void)
> Â{
> Â Â Â Âreturn bcm63xx_cpu_id;
> @@ -92,20 +101,19 @@ unsigned int bcm63xx_get_memory_size(void)
>
> Âstatic unsigned int detect_cpu_clock(void)
> Â{
> - Â Â Â unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
> -
> - Â Â Â /* BCM6338 has a fixed 240 Mhz frequency */
> - Â Â Â if (BCMCPU_IS_6338())
> + Â Â Â switch (bcm63xx_get_cpu_id()) {
> + Â Â Â case BCM6338_CPU_ID:
> + Â Â Â Â Â Â Â /* BCM6338 has a fixed 240 Mhz frequency */
> Â Â Â Â Â Â Â Âreturn 240000000;
>
> - Â Â Â /* BCM6345 has a fixed 140Mhz frequency */
> - Â Â Â if (BCMCPU_IS_6345())
> + Â Â Â case BCM6345_CPU_ID:
> + Â Â Â Â Â Â Â /* BCM6345 has a fixed 140Mhz frequency */
> Â Â Â Â Â Â Â Âreturn 140000000;
>
> - Â Â Â /*
> - Â Â Â Â* frequency depends on PLL configuration:
> - Â Â Â Â*/
> - Â Â Â if (BCMCPU_IS_6348()) {
> + Â Â Â case BCM6348_CPU_ID:
> + Â Â Â {
> + Â Â Â Â Â Â Â unsigned int tmp, n1, n2, m1;
> +
> Â Â Â Â Â Â Â Â/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
> Â Â Â Â Â Â Â Âtmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
> Â Â Â Â Â Â Â Ân1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
> @@ -114,17 +122,47 @@ static unsigned int detect_cpu_clock(void)
> Â Â Â Â Â Â Â Ân1 += 1;
> Â Â Â Â Â Â Â Ân2 += 2;
> Â Â Â Â Â Â Â Âm1 += 1;
> + Â Â Â Â Â Â Â return (16 * 1000000 * n1 * n2) / m1;
> Â Â Â Â}
>
> - Â Â Â if (BCMCPU_IS_6358()) {
> + Â Â Â case BCM6358_CPU_ID:
> + Â Â Â {
> + Â Â Â Â Â Â Â unsigned int tmp, n1, n2, m1;
> +
> Â Â Â Â Â Â Â Â/* 16MHz * N1 * N2 / M1_CPU */
> Â Â Â Â Â Â Â Âtmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
> Â Â Â Â Â Â Â Ân1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
> Â Â Â Â Â Â Â Ân2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
> Â Â Â Â Â Â Â Âm1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
> + Â Â Â Â Â Â Â return (16 * 1000000 * n1 * n2) / m1;
> Â Â Â Â}
>
> - Â Â Â return (16 * 1000000 * n1 * n2) / m1;
> + Â Â Â case BCM6368_CPU_ID:
> + Â Â Â {
> + Â Â Â Â Â Â Â unsigned int tmp, p1, p2, ndiv, m1;
> +
> + Â Â Â Â Â Â Â /* (64MHz / P1) * P2 * NDIV / M1_CPU */
> + Â Â Â Â Â Â Â tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
> +
> + Â Â Â Â Â Â Â p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
> + Â Â Â Â Â Â Â Â Â Â Â DMIPSPLLCFG_6368_P1_SHIFT;
> +
> + Â Â Â Â Â Â Â p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
> + Â Â Â Â Â Â Â Â Â Â Â DMIPSPLLCFG_6368_P2_SHIFT;
> +
> + Â Â Â Â Â Â Â ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
> + Â Â Â Â Â Â Â Â Â Â Â DMIPSPLLCFG_6368_NDIV_SHIFT;
> +
> + Â Â Â Â Â Â Â tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
> + Â Â Â Â Â Â Â m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
> + Â Â Â Â Â Â Â Â Â Â Â DMIPSPLLDIV_6368_MDIV_SHIFT;
> +
> + Â Â Â Â Â Â Â return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
> + Â Â Â }
> +
> + Â Â Â default:
> + Â Â Â Â Â Â Â BUG();
> + Â Â Â }
> Â}
>
> Â/*
> @@ -146,7 +184,7 @@ static unsigned int detect_memory_size(void)
> Â Â Â Â Â Â Â Âbanks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
> Â Â Â Â}
>
> - Â Â Â if (BCMCPU_IS_6358()) {
> + Â Â Â if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
> Â Â Â Â Â Â Â Âval = bcm_memc_readl(MEMC_CFG_REG);
> Â Â Â Â Â Â Â Ârows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
> Â Â Â Â Â Â Â Âcols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
> @@ -191,9 +229,15 @@ void __init bcm63xx_cpu_init(void)
> Â Â Â Â Â Â Â Âbcm63xx_irqs = bcm96345_irqs;
> Â Â Â Â Â Â Â Âbreak;
> Â Â Â Âcase CPU_BMIPS4350:
> - Â Â Â Â Â Â Â expected_cpu_id = BCM6358_CPU_ID;
> - Â Â Â Â Â Â Â bcm63xx_regs_base = bcm96358_regs_base;
> - Â Â Â Â Â Â Â bcm63xx_irqs = bcm96358_irqs;
> + Â Â Â Â Â Â Â if ((read_c0_prid() & 0xf0) == 0x0030) {
> + Â Â Â Â Â Â Â Â Â Â Â expected_cpu_id = BCM6368_CPU_ID;
> + Â Â Â Â Â Â Â Â Â Â Â bcm63xx_regs_base = bcm96368_regs_base;
> + Â Â Â Â Â Â Â Â Â Â Â bcm63xx_irqs = bcm96368_irqs;
> + Â Â Â Â Â Â Â } else {
> + Â Â Â Â Â Â Â Â Â Â Â expected_cpu_id = BCM6358_CPU_ID;
> + Â Â Â Â Â Â Â Â Â Â Â bcm63xx_regs_base = bcm96358_regs_base;
> + Â Â Â Â Â Â Â Â Â Â Â bcm63xx_irqs = bcm96358_irqs;
> + Â Â Â Â Â Â Â }
You might want to change that to an explicitly check for the BCM6358 -
at least mine evaluates to 0x0010, while for my BCM6328 it does to
0x0070.
> Â Â Â Â Â Â Â Âbreak;
> Â Â Â Â}
>
> diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
> index c2963da..d6e42c6 100644
> --- a/arch/mips/bcm63xx/dev-uart.c
> +++ b/arch/mips/bcm63xx/dev-uart.c
> @@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
> Â Â Â Âif (id >= ARRAY_SIZE(bcm63xx_uart_devices))
> Â Â Â Â Â Â Â Âreturn -ENODEV;
>
> - Â Â Â if (id == 1 && !BCMCPU_IS_6358())
> + Â Â Â if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
No need for brackets around the CPU checks (but I didn't find anything
in the code style documentation about this).
> Â Â Â Â Â Â Â Âreturn -ENODEV;
>
> Â Â Â Âif (id == 0) {
> diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
> index f2d5e30..f111ccd 100644
> --- a/arch/mips/bcm63xx/irq.c
> +++ b/arch/mips/bcm63xx/irq.c
> @@ -59,6 +59,14 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
> Â#define ext_irq_start     Â(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
> Â#define ext_irq_end      Â(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
> Â#endif
> +#ifdef CONFIG_BCM63XX_CPU_6368
> +#define irq_stat_reg      PERF_IRQSTAT_6368_REG
> +#define irq_mask_reg      PERF_IRQMASK_6368_REG
> +#define irq_bits        64
> +#define is_ext_irq_cascaded  Â1
> +#define ext_irq_start     Â(BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
> +#define ext_irq_end      Â(BCM_6368_EXT_IRQ3 - IRQ_INTERNAL_BASE)
This is different from ...
> +#endif
>
> Â#if irq_bits == 32
> Â#define dispatch_internal           Â__dispatch_internal
> @@ -116,6 +124,14 @@ static void bcm63xx_init_irq(void)
> Â Â Â Â Â Â Â Âext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
> Â Â Â Â Â Â Â Âext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
> Â Â Â Â Â Â Â Âbreak;
> + Â Â Â case BCM6368_CPU_ID:
> + Â Â Â Â Â Â Â irq_stat_addr += PERF_IRQSTAT_6368_REG;
> + Â Â Â Â Â Â Â irq_mask_addr += PERF_IRQMASK_6368_REG;
> + Â Â Â Â Â Â Â irq_bits = 64;
> + Â Â Â Â Â Â Â is_ext_irq_cascaded = 1;
> + Â Â Â Â Â Â Â ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
> + Â Â Â Â Â Â Â ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
... this one - you should fix the non runtime detection case.
> + Â Â Â Â Â Â Â break;
> Â Â Â Âdefault:
> Â Â Â Â Â Â Â ÂBUG();
> Â Â Â Â}
You are missing in bcm63xx_external_irq_mask,
bcm63xx_external_irq_unmask and bcm63xx_external_irq_clear special
handling for 6368's external IRQs. According to the Broadcom sources,
PERF_EXTIRQ_CFG_REG is at 0x18 for the 6368; for IRQ4 and IRQ5 it's at
0x1c.
> diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
> index be252ef..99d7f40 100644
> --- a/arch/mips/bcm63xx/prom.c
> +++ b/arch/mips/bcm63xx/prom.c
> @@ -32,9 +32,12 @@ void __init prom_init(void)
> Â Â Â Â Â Â Â Âmask = CKCTL_6345_ALL_SAFE_EN;
> Â Â Â Âelse if (BCMCPU_IS_6348())
> Â Â Â Â Â Â Â Âmask = CKCTL_6348_ALL_SAFE_EN;
> - Â Â Â else
> - Â Â Â Â Â Â Â /* BCMCPU_IS_6358() */
> + Â Â Â else if (BCMCPU_IS_6358())
> Â Â Â Â Â Â Â Âmask = CKCTL_6358_ALL_SAFE_EN;
> + Â Â Â else if (BCMCPU_IS_6368())
> + Â Â Â Â Â Â Â mask = CKCTL_6368_ALL_SAFE_EN;
> + Â Â Â else
> + Â Â Â Â Â Â Â mask = 0;
>
> Â Â Â Âreg = bcm_perf_readl(PERF_CKCTL_REG);
> Â Â Â Âreg &= ~mask;
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> index ce6b3ca..cf145ea 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> @@ -13,6 +13,7 @@
> Â#define BCM6345_CPU_ID Â Â Â Â 0x6345
> Â#define BCM6348_CPU_ID Â Â Â Â 0x6348
> Â#define BCM6358_CPU_ID Â Â Â Â 0x6358
> +#define BCM6368_CPU_ID Â Â Â Â 0x6368
>
> Âvoid __init bcm63xx_cpu_init(void);
> Âu16 __bcm63xx_get_cpu_id(void);
> @@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
> Â# define BCMCPU_IS_6358() Â Â Â(0)
> Â#endif
>
> +#ifdef CONFIG_BCM63XX_CPU_6368
> +# ifdef bcm63xx_get_cpu_id
> +# Âundef bcm63xx_get_cpu_id
> +# Âdefine bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
> +# Âdefine BCMCPU_RUNTIME_DETECT
> +# else
> +# Âdefine bcm63xx_get_cpu_id() BCM6368_CPU_ID
> +# endif
> +# define BCMCPU_IS_6368() Â Â Â(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
> +#else
> +# define BCMCPU_IS_6368() Â Â Â(0)
> +#endif
> +
> Â#ifndef bcm63xx_get_cpu_id
> Â#error "No CPU support configured"
> Â#endif
> @@ -309,6 +323,47 @@ enum bcm63xx_regs_set {
> Â#define BCM_6358_PCMDMAS_BASE Â Â Â Â Â(0xfffe1a00)
>
>
> +/*
> + * 6368 register sets base address
> + */
> +#define BCM_6368_DSL_LMEM_BASE Â Â Â Â (0xdeadbeef)
0xb0f80000 ;-)
> +#define BCM_6368_PERF_BASE Â Â Â Â Â Â (0xb0000000)
> +#define BCM_6368_TIMER_BASE Â Â Â Â Â Â(0xb0000040)
> +#define BCM_6368_WDT_BASE Â Â Â Â Â Â Â(0xb000005c)
> +#define BCM_6368_UART0_BASE Â Â Â Â Â Â(0xb0000100)
> +#define BCM_6368_UART1_BASE Â Â Â Â Â Â(0xb0000120)
> +#define BCM_6368_GPIO_BASE Â Â Â Â Â Â (0xb0000080)
> +#define BCM_6368_SPI_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6368_SPI2_BASE Â Â Â Â Â Â (0xb0000800)
> +#define BCM_6368_UDC0_BASE Â Â Â Â Â Â (0xdeadbeef)
> +#define BCM_6368_OHCI0_BASE Â Â Â Â Â Â(0xb0001600)
> +#define BCM_6368_OHCI_PRIV_BASE Â Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6368_USBH_PRIV_BASE Â Â Â Â Â Â Â Â(0xb0001700)
> +#define BCM_6368_MPI_BASE Â Â Â Â Â Â Â(0xb0001000)
> +#define BCM_6368_PCMCIA_BASE Â Â Â Â Â (0xb0001054)
> +#define BCM_6368_SDRAM_REGS_BASE Â Â Â (0xdeadbeef)
> +#define BCM_6368_M2M_BASE Â Â Â Â Â Â Â(0xdeadbeef)
> +#define BCM_6368_DSL_BASE Â Â Â Â Â Â Â(0xdeadbeef)
0xb0f56000
Jonas
