MIPS hardware performance counters may have either 32-bit or 64-bit
wide counter registers. The current implementation only supports the
32-bit variety.
These patches aim to add support for 64-bit wide counters while
mantaining support for 32-bit.
Tested with perf top and perf record, which both work well on an
Octeon/Debian based system.
Changes from v3:
o Rebased against 2.6.39.
o Re-Include Octeon processor support.
Changes from v2:
o Quit sign extending 32-bit counter values.
o Remove usless local_irq_save() in several places.
Changes from v1:
o Removed Octeon processor support to a separate patch set.
o Rebased against v5 of Deng-Cheng Zhu's cleanups:
http://patchwork.linux-mips.org/patch/2011/
http://patchwork.linux-mips.org/patch/2012/
http://patchwork.linux-mips.org/patch/2013/
http://patchwork.linux-mips.org/patch/2014/
http://patchwork.linux-mips.org/patch/2015/
o Tried to fix problem where 32-bit counters generated way too many
interrupts.
David Daney (5):
MIPS: Add accessor macros for 64-bit performance counter registers.
MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
MIPS: perf: Reorganize contents of perf support files.
MIPS: perf: Add support for 64-bit perf counters.
MIPS: perf: Add Octeon support for hardware perf.
arch/mips/Kconfig | 2 +-
arch/mips/include/asm/mipsregs.h | 8 +
arch/mips/kernel/Makefile | 5 +-
arch/mips/kernel/perf_event.c | 521 +--------------
arch/mips/kernel/perf_event_mipsxx.c | 1267 ++++++++++++++++++++++++---------
5 files changed, 935 insertions(+), 868 deletions(-)
Cc: Deng-Cheng Zhu <dengcheng.zhu@xxxxxxxxx>
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1.7.2.3
