Hi Ralf, Have you got time to look into this issue. Regards On Tue, Mar 29, 2011 at 11:24 AM, naveen yadav <yad.naveen@xxxxxxxxx> wrote: > I am sorry, Yes they are VIPT, > > > On Fri, Mar 25, 2011 at 10:57 PM, Ralf Baechle <ralf@xxxxxxxxxxxxxx> wrote: >> On Fri, Mar 25, 2011 at 02:38:13PM +0530, naveen yadav wrote: >> >>> We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our >>> cache is VIVT having cache aliasing . >> >> No, they're VIPT unless you successfully modified your 34K core to >> change it from a less than perfect cache design to the most lunatic >> cache policy known to man kind ... >> >>> When I check the implementation on ARM I can check the implemenation >>> exists , but there is not similar implementation exists on MIPS. >>> These API's are used by XFS module: >>> >>> static inline void flush_kernel_vmap_range(void *vaddr, int size) >>> static inline void invalidate_kernel_vmap_range(void *vaddr, int size) >>> static inline void flush_kernel_dcache_page(struct page *page) >> >> A known problem for (too ...) long. I'll finally take care of it. >> >> Ralf >> >
