On 02/22/2011 04:07 PM, David Gibson wrote:
On Tue, Feb 22, 2011 at 12:57:46PM -0800, David Daney wrote:
Signed-off-by: David Daney<ddaney@xxxxxxxxxxxxxxxxxx>
---
arch/mips/cavium-octeon/.gitignore | 2 +
arch/mips/cavium-octeon/Makefile | 13 ++
arch/mips/cavium-octeon/octeon_3xxx.dts | 314 +++++++++++++++++++++++++++++++
arch/mips/cavium-octeon/octeon_68xx.dts | 99 ++++++++++
4 files changed, 428 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/cavium-octeon/.gitignore
create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts
create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts
[...]
+ };
+ };
Uh.. where are the CPUs?
The number and type of CPUs can be (and is) probed. There is an
existing mechanism for the bootloader to communicate which CPUs should
be used.
Likewise for memory, there is an existing mechanism for the bootloader
to communicate which memory should be used.
It is possible that in the future, we would want to put CPUs and Memory
in the Device Tree. If we do, we can add that without having to disturb
the 'soc' device bindings.
My main motivation for this first patch set is to get sane bindings for
all the 'soc' devices And to that end, your feedback has been quite useful.
Thanks,
David Daney
