No, it just means that there is special hardware to detect aliases and handle them as if the addresses were not aliased.
-----Original Message-----
From: linux-mips-bounce@xxxxxxxxxxxxxx on behalf of COLin
Sent: Fri 1/21/2011 12:52 AM
To: ralf@xxxxxxxxxxxxxx; linux-mips@xxxxxxxxxxxxxx
Subject: 24k data cache, PIPT or VIPT?
Hi all,
I found that there is this information while Linux is booting:
[Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes]
I thought the latest MIPS CPUs all use VIPT. I didn't find anything about PIPT on 24k Software User's Manual, either.
The code related to this is here:
case CPU_24K:
case CPU_34K:
case CPU_74K:
case CPU_1004K:
if ((read_c0_config7() & (1 << 16))) {
/* effectively physically indexed dcache,
thus no virtual aliases. */
c->dcache.flags |= MIPS_CACHE_PINDEX;
break;
The 16's bit of config 7 register:
[Alias removed: This bit indicates that the data cache is organized to
avoid virtual aliasing problems. This bit is only set if the data cache
config and MMU type would normally cause aliasing - i.e., only for
the 32KB and larger data cache and TLB-based MMU.]
Does it imply that the CPU is using PIPT?
Thanks and regards,
Colin
