Octeon and Octeon2 have scratch memory, and/or scratch registers that allow us to save some instructions in the TLB refill handler. Octeon2 has indexed load instructions that also can help. The first patch adds uASM support for the indexed loads. The second essentially hand codes the refill handler with a view to optimally scheduling the instructions to reduce stalls and increase the number of dual issue slots that can be filled. David Daney (2): MIPS: Add LDX and LWX instructions to uasm. MIPS: Optimize TLB handlers for Octeon CPUs arch/mips/include/asm/inst.h | 14 ++ arch/mips/include/asm/uasm.h | 4 + arch/mips/mm/tlbex.c | 361 ++++++++++++++++++++++++++++++++++++------ arch/mips/mm/uasm.c | 7 +- 4 files changed, 334 insertions(+), 52 deletions(-) -- 1.7.2.3
