On Tue, Nov 23, 2010 at 10:26:44AM -0800, Kevin Cernekee wrote: > write_c0_compare(read_c0_count()); > > Even if the counter doesn't increment during execution, this might not > generate an interrupt until the counter wraps around. The CPU may > perform the comparison each time CP0 COUNT increments, not when CP0 > COMPARE is written. > > If mips_next_event() is called with a very small delta, and CP0 COUNT > increments during the calculation of "cnt += delta", it is possible > that CP0 COMPARE will be written with the current value of CP0 COUNT. > If this is detected, the function should return -ETIME, to indicate > that the interrupt might not have actually gotten scheduled. Good catch - though on real hardware it should be theoretical as the minimum timer interval is 300ns. So it should only be trigerable on a very slow system like a hardware emulator or maybe if a software emulator like qemu gets rescheduled between the update and the read-back. Applied, Ralf
