On 10/25/2010 08:37 AM, Ardelean, Andrei wrote:
Hi David,
I studied this driver and few other examples and I have one question
regarding the driver configuration:
Which field must be initialized in the plat_serial8250_port structure:
unsigned long iobase; /* io base address */
void __iomem *membase; /* ioremap cookie or NULL */
resource_size_t mapbase; /* resource base */
Some drivers init only one of them, other two fields.
My UART is located at 0x1bf01000, can I put this value in all those
fields?
As with many things in life, it depends.
In this case it depends on the flags you pass as well as any serial_in()
and serial_out() functions you may have. It is fortunate you have the
source code available, you can use it to see how the different options
affect things.
David Daney
Thanks,
Andrei
-----Original Message-----
From: David Daney [mailto:ddaney@xxxxxxxxxxxxxxxxxx]
Sent: Friday, October 22, 2010 3:31 PM
To: Ardelean, Andrei
Cc: linux-mips@xxxxxxxxxxxxxx
Subject: Re: Is it any serial8250 platform driver available?
On 10/22/2010 12:23 PM, Ardelean, Andrei wrote:
Hi,
I am porting MIPS Linux from MALTA to a new board. I ported early
console code from malta_console.c and I am looking now to use a
interrupt driven driver for TTY. My UART is compatible with 8250 (1
UART
port only) but the UART registers are directly mapped in CPU memory
map.
There is no PCI bus. My problem is that the driver implemented in
8250.c
is very complex and it seems to be hardcode for ISA bus, is it any
simple platform UART driver available to be directly mapped in the CPU
space? Can you give me some advice what would be a good approach for
my
case?
Many chips have 8250 compatible ports and use 8250.c.
See arch/mips/cavium-octeon/serial.c
David Daeny
