On Wed, Oct 20, 2010 at 08:05:42PM -0700, Kevin Cernekee wrote: > On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates > that the L2 cache is disabled and therefore Linux should not attempt > to use it. I did a bit of research in the meantime. Turns out that some MIPS customers are using their own L2 cache controller. That means a simple check by the CPU PrID is not sufficient and we will need some sort of platform-specific probe, sigh. I've moved all the code your patch adds to a separate function and added a comment so at least people working on platforms with different L2 conntrollers will have a small chance of figuring out what mine blew up under their feet. Ralf
