The creation of the I/O clock domain requires some adjustments. Since the CF bus timing logic is clocked by the I/O clock, use its rate for delay calculations. Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx> Cc: Jeff Garzik <jgarzik@xxxxxxxxx> Cc: linux-ide@xxxxxxxxxxxxxxx --- drivers/ata/pata_octeon_cf.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c index 06ddd91..74b8298 100644 --- a/drivers/ata/pata_octeon_cf.c +++ b/drivers/ata/pata_octeon_cf.c @@ -60,7 +60,7 @@ static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs) * Compute # of eclock periods to get desired duration in * nanoseconds. */ - val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000), + val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000), 1000 * tim_mult); return val; -- 1.7.2.3
