Yang Shi 写道:
Ralf Baechle 写道:
On Fri, May 14, 2010 at 06:29:07PM +0800, Yang Shi wrote:
I'm running 2.6.34-rc7 mainline kernel on SB1250 (Rev B2) board. And, I
use the default sb1250 kernel config (sb1250-swarm_defconfig). So, 64
bit kernel is used. During kernel loading module got bus error, see
below log:
Whops. Fixes which were supposed to handle exactly this problem went
upstream for 2.6.34-rc3 and were tested successfully by others on their
systems.
I wonder if in arch/mips/sibyte/sb1250/setup.c you can instrument
the function sb1250_m3_workaround_needed() and print the values of
soc_type, soc_pass and the retun value of that function. Then let's take
it from there.
See below log:
Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2)
And, soc_typs is 0x0 and soc_pass is 0x11, sb1250_m3_workaround_needed
should return 1. So, tlb refill handler should go the m3 workaround code
path.
It seems CPU_PREFETCH caused this issue. See commit:
commit 6b4caed2ebff4ee232f227d62eb3180d0b558a31
Author: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Date: Wed Jan 28 17:48:40 2009 +0000
MIPS: IP27: Switch from DMA_IP27 to DMA_COHERENT
commit 0d356eaa6316cbb3e89b4607de20b2f2d0ceda25 from linux-mips
The special IP27 DMA code selected by DMA_IP27 has been removed a while
ago turning DMA_IP27 into almost a nop. Also fixup the broken logic of
its last users memcpy.S and memcpy-inatomic.s.
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
If undef CPU_PREFETCH for SB1250, module can be loaded correctly.
Thanks,
Yang
Thanks,
Yang
Ralf
