2010/5/5 Jamie Iles <jamie.iles@xxxxxxxxxxxx>: > On Wed, May 05, 2010 at 09:55:34PM +0800, Deng-Cheng Zhu wrote: >> This patch is the HW perf event support. To enable this feature, we can >> not choose the SMTC kernel; Oprofile should be disabled; kernel >> performance events be selected. Then we can enable it in Kernel type menu. >> >> Oprofile for MIPS platforms initializes irq at arch init time. Currently >> we do not change this logic to allow PMU reservation. >> >> If a platform has EIC, we can use the irq base and perf counter irq >> offset defines for the interrupt controller in mipspmu_get_irq(). >> >> Besides generic hardware events and cache events, raw events are also >> supported by this patch. Please refer to processor core software user's >> manual and the comments for mipsxx_pmu_map_raw_event() for more details. > > This looks good to me. I'm not familiar with MIPS so I can't offer many > comments in that respect but as a general question, is there a reason that > OProfile can't be enabled as well? In ARM we have a method to reserve the PMU > so that we can build both but only one can run at the same time. Recently, > Will Deacon has posted a patch series that makes OProfile use perf events > as the counter backend so you could even use both at the same time. > > Jamie > Hi, Jamie Thanks for your review! Yes, I noticed ARM had a PMU reservation mechanism between Oprofile and Perf. It's a run-time method (irqs are requested/freed in start/stop), not an arch init method (requested/freed in init/exit). And this mechanism is great for sure. But in current MIPS/Oprofile code, this is done in init/exit. MIPS/Oprofile authors may have special concerns to do so. So I'm adding Zhangjin and Ralf in the TO-list, hoping to hear more comments about this. To reduce the risk introduced by changing this mechanism, I didn't add the PMU reservation/sharing and placed an extra comment in this patch's introduction (see above). Deng-Cheng
