From: Wu Zhangjin <wuzhangjin@xxxxxxxxx>
Changes from v1:
o use the new interface mips_cyc2ns() intead of the old
mips_sched_clock().
The commit "MIPS: add a common mips_cyc2ns()" have abstracted the
solution of the 64bit calculation's overflow problem into a common
mips_cyc2ns() function in arch/mips/include/asm/time.h, This patch just
rewrites the sched_clock() for cavium-octeon on it.
Signed-off-by: Wu Zhangjin <wuzhangjin@xxxxxxxxx>
---
arch/mips/cavium-octeon/csrc-octeon.c | 29 ++---------------------------
1 files changed, 2 insertions(+), 27 deletions(-)
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 0bf4bbe..bca0004 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -52,34 +52,9 @@ static struct clocksource clocksource_mips = {
unsigned long long notrace sched_clock(void)
{
- /* 64-bit arithmatic can overflow, so use 128-bit. */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
- u64 t1, t2, t3;
- unsigned long long rv;
- u64 mult = clocksource_mips.mult;
- u64 shift = clocksource_mips.shift;
- u64 cnt = read_c0_cvmcount();
+ u64 cyc = read_c0_cvmcount();
- asm (
- "dmultu\t%[cnt],%[mult]\n\t"
- "nor\t%[t1],$0,%[shift]\n\t"
- "mfhi\t%[t2]\n\t"
- "mflo\t%[t3]\n\t"
- "dsll\t%[t2],%[t2],1\n\t"
- "dsrlv\t%[rv],%[t3],%[shift]\n\t"
- "dsllv\t%[t1],%[t2],%[t1]\n\t"
- "or\t%[rv],%[t1],%[rv]\n\t"
- : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
- : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
- : "hi", "lo");
- return rv;
-#else
- /* GCC > 4.3 do it the easy way. */
- unsigned int __attribute__((mode(TI))) t;
- t = read_c0_cvmcount();
- t = t * clocksource_mips.mult;
- return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
+ return mips_cyc2ns(cyc, clocksource_mips.mult, clocksource_mips.shift);
}
void __init plat_time_init(void)
--
1.7.0.1
