Since commit 656be92f aka "Load modules to CKSEG0 if CONFIG_BUILD_ELF64=n" module support is broken on 64bit. Since then modules arr loaded into 32bit compat adresses which are sign extended 64bit addresses. The SiByte war handler was not updated and those addresses were not recognized by the TLB hadling. This patch fixes this by shifting away the upper bits including the R and Fill bits. Now we compare VPN2 of C0_ENTRYHI against the matching bits at C0_BADVADDR. Cc: <stable@xxxxxxxxxx> Signed-off-by: Sebastian Andrzej Siewior <sebastian@xxxxxxxxxxxxx> --- arch/mips/mm/tlbex.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index badcf5e..47faeb4 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -745,6 +745,10 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) UASM_i_MFC0(&p, K1, C0_ENTRYHI); uasm_i_xor(&p, K0, K0, K1); UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); +#ifdef CONFIG_64BIT + /* Make sure we have here just VPN2 */ + uasm_i_dsll32(&p, K0, K0, PAGE_SHIFT + 1 + 24 - 32); +#endif uasm_il_bnez(&p, &r, K0, label_leave); /* No need for uasm_i_nop */ } @@ -1264,6 +1268,10 @@ static void __cpuinit build_r4000_tlb_load_handler(void) UASM_i_MFC0(&p, K1, C0_ENTRYHI); uasm_i_xor(&p, K0, K0, K1); UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); +#ifdef CONFIG_64BIT + /* Make sure we have here just VPN2 */ + uasm_i_dsll32(&p, K0, K0, PAGE_SHIFT + 1 + 24 - 32); +#endif uasm_il_bnez(&p, &r, K0, label_leave); /* No need for uasm_i_nop */ } -- 1.6.6
